1. Field of the Invention
The present invention relates to radio frequency communications, and in particular to a method and circuit for generating a variable frequency clock signal from a crystal oscillator, and for adjusting the frequency of the variable clock signal to compensate for carrier frequency and sampling rate errors.
2. Description of the Prior Art
Mobile telephones have become a normal part of everyday life. However, there are competing standards for mobile telephone networks around the world. Today, two important digital mobile network systems are the Global System for Mobile communications (GSM) and Wideband Code Division Multiple Access (WCDMA). These two systems use different techniques for channel allocation on the broadcast network, and they use different carrier frequencies. In communications systems, carrier frequencies are derived from a reference timing signal clock which is generated by a crystal oscillator. The same oscillator is also used as a reference clock for the analog-to-digital converter (ADC) and the digital-to-analog converter (DAC) which interface the analog and digital circuits in the system. However, because the crystal oscillator has limited precision, the carrier frequency and the ADC sampling rate may deviate from their nominal values. In some communications systems (e.g., CDMA), it is necessary to compensate for these deviations in order for the system to function properly.
In a dual system supporting both GSM and WCDMA communications, two clock frequencies are required to drive the receiving and transmitting electronics in mobile telephones: a 13 MHz clock for the GSM subsystem, and a 15.36 MHz clock for the WCDMA subsystem. A WCDMA subsystem also compensates for the carrier and sampling frequency offsets described above.
It is not always practical to provide two crystal oscillators to generate dual clock frequencies in a mobile telephone. Existing systems use a single, voltage-controlled, temperature-compensated crystal oscillator for the first clock, and derive the second clock from a second voltage-controlled oscillator driven by a phase-locked loop (PLL) using the first clock as a reference clock. The second frequency may be tuned by fine adjustments of the control voltage of the voltage-controlled oscillator. However, the tuning speed is limited by the settling times of the PLL and voltage adjustment circuits. When the greatest common divisor of the two clock frequencies is low (e.g., 40 kHz for 13 MHz and 15.36 MHz), the PLL settling time is long, and the system performance is degraded. Furthermore, the high resolution required in the control voltage circuit increases the system cost. It is desired, therefore, to provide a system for accurately and rapidly generating a second clock frequency from a first clock frequency, or at least provide a useful alternative.